Apparatus for generating reference voltage in semiconductor memory apparatus

ABSTRACT

An apparatus for generating a reference voltage in a semiconductor memory apparatus according includes: a first voltage generating unit that generates a voltage proportional to temperature; a second voltage generating unit that generates a voltage inversely proportional to temperature; and a reference voltage generating unit that adjusts the amount of current in the first voltage generating unit or the second voltage generating unit on the basis of a control signal, and outputs a constant reference voltage regardless of a variation in temperature. The apparatus can generate a constant reference voltage regardless of a variation in temperature and mismatch between elements. Thus, it is possible to improve the performance and reliability of a system using the apparatus to a maximum.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor memory apparatus, andmore particularly, to an apparatus for generating a reference voltage ina semiconductor memory apparatus.

2. Related Art

As shown in FIG. 1, an apparatus for generating a reference voltage in asemiconductor memory apparatus according to the related art includes afirst voltage generating unit 10 for generating a voltage that isproportional to temperature, a second voltage generating unit 20 forgenerating a voltage that is inversely proportional to temperature, acurrent mirror including a transistor M1 having a source connected to apower supply terminal of the first voltage generating unit 10 and atransistor K1 having a source connected to a power supply terminal ofthe second voltage generating unit 20, and a resistor R3 that has oneend connected to the drains of the transistors M1 and K1 and the otherend connected to the ground, and that outputs a reference voltage VREF.

The operation of the apparatus according to the related art will bedescribed below.

The first voltage generating unit 10 for generating a voltageproportional to temperature is a bandgap-type circuit, and generates avoltage using a difference in base-emitter voltage (VBE) of a bipolarjunction transistor (BJT). The difference in base-emitter voltage isproportional to a thermal voltage (VT) When the thermal voltage isdifferentiated with respect to temperature, the differentiated value hasa positive temperature coefficient. For example, the positivetemperature coefficient may be 0.087 mV/K. In this case, VT=kT/q, wherek is the Boltzmann constant (1.380622×10⁻²³ J·K⁻¹), T is an absolutetemperature, and q=1.6×10⁻¹⁹C.

Meanwhile, the second voltage generating unit 20 for generating avoltage inversely proportional to temperature has the same voltagegenerating method as the first voltage generating unit 10 for generatinga voltage proportional to temperature. In this case, the second voltagegenerating unit 20 has a negative temperature coefficient of, forexample, −2.1 mV/K.

The above-mentioned temperature coefficient is just an illustrativeexample. Both the first voltage generating unit 10 for generating avoltage proportional to temperature and the second voltage generatingunit 20 for generating a voltage inversely proportional to temperatureuse bipolar junction transistors, and the absolute value of thetemperature coefficient of the second voltage generating unit 20 forgenerating a voltage inversely proportional to temperature isconsiderably larger than that of the first voltage generating unit 10for generating a voltage proportional to temperature.

As described above, a current having a zero temperature coefficient(ZTC), that is, a current that is constant regardless of temperature isgenerated by combining the output of the first voltage generating unit10 for generating a voltage proportional to temperature with the outputof the second voltage generating unit 20 for generating a voltageinversely proportional to temperature using a coefficient of the currentmirror, that is, the ratio (XM:XK) of the size of the transistor Ml andthe size of the transistor K1.

In addition, the current having ZTC passes through the resistor R3,which causes a constant reference voltage to be generated regardless oftemperature.

The reference voltage VREF can be expressed as follows: VREF=M*R3/R1(VT*1 nN)+K*R3/R2*VBE.

In the above-mentioned expression, M and K are coefficients of thetransistors M1 and K1 forming the current mirror, and may vary whenmismatching occurs in the circuit design or vary due to the differencebetween element characteristics even when mismatching does not occur,which may have an effect on ZTC. In addition, N is a coefficient of thebipolar junction transistor.

Considering the offset voltages VOFFSET of operational amplifiers 11 and21 of the first voltage generating unit 10 for generating a voltageproportional to temperature and the second voltage generating unit 20for generating a voltage inversely proportional to temperature, thereference voltage VREF can be expressed as follows: VREF=M*R3/R1 (VT*1nN)+K*R3/R2*VBE+M*R3/R1*VOFFSET+K*R3/R2*VOFFSET.

As can be seen from the above-mentioned expression, according to therelated art, the offset voltages of the operational amplifiers as wellas the coefficients M and K of the transistors have an effect on ZTC. Asa factor included in the expression, the resistor R3 for outputting avoltage has a temperature coefficient, which may have an effect on ZTC.

As described above, in the apparatus for generating a reference voltagein a semiconductor memory apparatus according to the related art, it isdifficult to generate a constant reference voltage regardless of avariation in temperature due to current control elements having fixedtemperature coefficients and various factors, such as the offsetvoltages of the operational amplifiers and the resistor. As a result,the related art has a problem in that the reference voltage is unstable,which causes the performance and reliability of a system using theapparatus for generating a reference voltage in a semiconductor memoryapparatus to deteriorate.

SUMMARY

Embodiments of the present invention provide an apparatus for generatinga reference voltage in a semiconductor memory apparatus capable ofgenerating a constant reference voltage regardless of a variation intemperature and a mismatch between elements.

According to an embodiment of the present invention, there is providedan apparatus for generating a reference voltage in a semiconductormemory apparatus. The apparatus includes: a first voltage generatingunit that generates a voltage proportional to temperature; a secondvoltage generating unit that generates a voltage inversely proportionalto temperature; and a reference voltage generating unit that adjusts theamount of current in the first voltage generating unit or the secondvoltage generating unit on the basis of a control signal, and outputs aconstant reference voltage regardless of a variation in temperature.

According to another embodiment of the present invention, there isprovided an apparatus for generating a reference voltage in asemiconductor memory apparatus. The apparatus includes: a first voltagegenerating unit that generates a voltage proportional to temperature; asecond voltage generating unit that generates a voltage inverselyproportional to temperature; and a reference voltage generating unitthat separately adjusts the amount of current in the first voltagegenerating unit and the second voltage generating unit on the basis offirst and second control signals and outputs a constant referencevoltage regardless of a variation in temperature.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram illustrating the structure of an apparatusfor generating a reference voltage in a semiconductor memory apparatusaccording to the related art.

FIG. 2 is a circuit diagram illustrating the structure of an apparatusfor generating a reference voltage in a semiconductor memory apparatusaccording to a first embodiment of the present invention.

FIG. 3 is a block diagram illustrating the structure of a control unitshown in FIG. 2.

FIG. 4A is a circuit diagram illustrating the structure of a firstsignal output unit show in FIG. 3.

FIG. 4B is a circuit diagram illustrating the structure of a secondsignal output unit show in FIG. 3.

FIG. 4C is a circuit diagram illustrating the structure of a thirdsignal output unit show in FIG. 3.

FIGS. 5A to 5D are graphs illustrating a method of adjusting a referencevoltage according to an exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram illustrating the structure of an apparatusfor generating a reference voltage in a semiconductor memory apparatusaccording to a second embodiment of the present invention.

FIG. 7A is a block diagram illustrating the structure of a first controlunit shown in FIG. 6.

FIG. 7B is a block diagram illustrating the structure of a secondcontrol unit shown in FIG. 6.

DESCRIPTION OF EXEMPLARY EMBODIMENT

Hereinafter, apparatuses for generating a reference voltage in asemiconductor memory apparatus according to preferred embodiments of thepresent invention will be described in detail with reference to theaccompanying drawings.

First Embodiment

As shown in FIG. 2, the apparatus for generating a reference voltage ina semiconductor memory apparatus according to the first embodiment ofthe present invention includes a first voltage generating unit 10 forgenerating a voltage proportional to temperature, a second voltagegenerating unit 20 for generating a voltage inversely proportional totemperature, and a reference voltage generating unit 300 that adjuststhe amount of current in the first voltage generating unit 10 or thesecond voltage generating unit 20 in response to a control signal, so asto output a constant voltage regardless of a variation in temperature.

The reference voltage generating unit 300 includes a first adjustingunit 310 that adjusts the amount of current in the first voltagegenerating unit 10, a second adjusting unit 320 that adjusts the amountof current in the second voltage generating unit 20, a control unit 330that outputs a selection signal for controlling the first adjusting unit310 or the second adjusting unit 320, and a reference voltage outputunit 340 that outputs a reference voltage based on the amount of currentadjusted by the first adjusting unit 310 and the amount of currentadjusted by the second adjusting unit 320.

The first adjusting unit 310 includes a plurality of current controlelements, that is, transistors M1 to M8 connected between a power supplyterminal of the first voltage generating unit 10 and the referencevoltage output unit 340 through switching elements SM1 to SM8. Thesecond adjusting unit 320 includes a plurality of current controlelements, that is, transistors K1 to K8 connected between a power supplyterminal of the second voltage generating unit 20 and the referencevoltage output unit 340 through switching elements SK1 to SK8. In thiscase, the switching elements SM1 to SM8 and SK1 to SK8 may be formed oftransistors each having a gate to which the selection signal output fromthe control unit 330 is input.

The transistors M1 to M8 of the first adjusting unit 310 have differentsizes, that is, different resistance values, and the transistor (forexample, M8) having an intermediate resistance value is set as areference transistor for generating an initial reference voltage.Similarly, the transistors K1 to K8 of the second adjusting unit 320have different sizes, that is, different resistance values, and thetransistor (for example, K8) having an intermediate resistance value isset as a reference transistor for generating an initial referencevoltage.

The resistance values of the transistors M1 to M8 and K1 to K8 arealready known to an operator, and the transistors M1 to M7 and K1 to K7other than the reference transistors M8 and K8 may be connected inseries to one another either in the ascending or descending order ofresistance values.

As described in the related art, the absolute value of a temperaturecoefficient (for example, −2.1 mV/K) of the second voltage generatingunit 20 is considerably larger than the absolute value of a temperaturecoefficient (for example, 0.087 mV/K) of the first voltage generatingunit 10. Therefore, since the first adjusting unit 310 adjusts theamount of current in the first voltage generating unit 10, it is used tofinely adjust a reference voltage. Since the second adjusting unit 320adjusts the amount of current in the second voltage generating unit 20,it is used to coarsely adjust a reference voltage.

As shown in FIG. 3, the control unit 330 includes a selecting unit 331that generates selection signals DEC1 to DEC7 for adjusting the amountof current in the first voltage generating unit 10 or the amount ofcurrent in the second voltage generating unit 20 by a predeterminedlevel on the basis of first control signals TM1 to TM3; a first signaloutput unit 332 that outputs the selection signals DEC1 to DEC7 to thefirst adjusting unit 310 or the second adjusting unit 320 on the basisof a second control signal; a second signal output unit 333 thatgenerates a first reference selection signal for driving the referencetransistor M8 of the first adjusting unit 310 on the basis of the firstcontrol signals TM1 to TM3 and the second control signal, and outputsthe generated first reference selection signal; and a third signaloutput unit 334 that generates a second reference selection signal fordriving the reference transistor K8 of the second adjusting unit 320 onthe basis of the first control signals TM1 to TM3 and the second controlsignal, and outputs the generated second reference selection signal.

The selecting unit 331 is a decoder. The selecting unit 331 converts thefirst control signal of 3 bits into a decimal value, changes a selectionsignal corresponding to the converted decimal value to a high level,changes the other selection signals to low levels, and outputs theselection signals. For example, when the first control signals TM1, TM2,and TM3 have binary values of 0, 0, and 1, respectively, and thus thedecimal value thereof is 1, the selection signal DEC1 is output at ahigh level, and the selection signals DEC2 to DEC7 are output at lowlevels. However, the decimal value of the first control signals is setto 0 (TM1=0, TM2=0, and TM3=0) during a default operation fordetermining an initial reference value. In this case, the selectionsignals DEC1 to DEC7 output from the selecting unit 331 are all at lowlevel.

Since the first signal output unit 332 has to output the selectionsignals DEC1 to DEC7 to the first adjusting unit 310 or the secondadjusting unit 320, seven circuit structures shown in FIG. 4A areneeded. FIG. 4A is a diagram illustrating an example of a circuitstructure for outputting the selection signal DEC1 among the selectionsignals. As shown in FIG. 4A, the circuit structure includes a firsttransfer element, that is a pass gate PG1, for outputting the selectionsignal DEC1 to the corresponding switching element SK1 of the secondadjusting unit 320 on the basis of the second control signal and aninverted signal of the second control signal that is inverted by a firstinverter IV1; and a second transfer element, that is a pass gate PG2,for outputting the selection signal DEC1 to the corresponding switchingelement SM1 of the first adjusting unit 310 on the basis of the secondcontrol signal, and the inverted signal of the second control signalthat is inverted by the first inverter IV1. In FIG. 4A, when the secondcontrol signal is at a low level, the first adjusting unit 310 isselected. On the other hand, when the second control signal is at a highlevel, the second adjusting unit 320 is selected. The selection of thefirst and second adjusting units 310 and 320 may be changed by a simplevariation in circuit structure.

As shown in FIG. 4B, the second signal output unit 333 is formed of alogic circuit that turns on the switching element SM8 connected to thereference transistor M8 of the first adjusting unit 310 when the decimalvalue of the first control signals is zero and when the second adjustingunit 320 is selected by the second control signal although the decimalvalue of the first control signals is not zero. The circuit structureshown in FIG. 4B includes a first NOR gate NOR1 to which the firstcontrol signals are input, a second NOR gate NOR2 to which the output ofthe first NOR gate NOR1 and the second control signal are input, and asecond inverter IV2 that inverts the output of the second NOR gate NOR2and outputs the inverted signal to the switching element SM8.

As shown in FIG. 4C, the third signal output unit 334 is formed of alogic circuit that turns on the switching element SK8 connected to thereference transistor K8 of the second adjusting unit 320 when thedecimal value of the first control signals is zero and when the firstadjusting unit 310 is selected by the second control signal although thedecimal value of the first control signals is not zero. The circuitstructure shown in FIG. 4C includes a third NOR gate NOR3 to which thefirst control signals are input, a fourth NOR gate NOR4 to which theoutput of the third NOR gate NOR3 and an inverted signal of the secondcontrol signal that is inverted by a third inverter IV3 are input, and afourth inverter IV4 that inverts the output of the fourth NOR gate NOR4and outputs the inverted signal to the switching element SK8.

The reference voltage output unit 340 (FIG. 2) includes a resistor R3having one end connected to both the first adjusting unit 310 and thesecond adjusting unit 320 and the other end connected to the ground towhich the first voltage generating unit 10 and the second voltagegenerating unit 20 are connected.

Next, the operation of the first embodiment having the above-mentionedstructure will be described below.

First, the operator determines whether a reference voltage VREFsatisfies a zero temperature coefficient (ZTC) in an initial statebefore an adjusting operation, that is, whether a target voltage isoutput regardless of temperature. Therefore, the logical values of thefirst control signals TM1, TM2, and TM3 are all set to zero, and thesecond control signal may have any level from the viewpoint of thecircuit structure shown in FIG. 3. In this case, a test mode may be usedto set the first control signals and the second control signal.

The selecting unit 331 shown in FIG. 3 outputs the output signals DEC1to DEC7 having low levels since the logical values of the first controlsignals TM1, TM2, and TM3 are all set to zero. Therefore, no signalshaving a high level are output from the first signal output unit 332 tothe switching elements SM1 to SM7 and SK1 to SK7.

Meanwhile, the first NOR gate NOR1 of the second signal output unit 333and the third NOR gate NOR3 of the third signal output unit 334 outputhigh-level signals since they receive the first control signals havinglogical values of 0. The second inverter IV2 of the second signal outputunit 333 and the fourth inverter IV4 of the third signal output unit 334output high-level signals to the switching element SM8 and SK8,respectively, regardless of the level of the second control signal.Then, the switching elements SM8 and SK8 are turned on, which causes thereference transistors M8 and K8 to be connected to the reference voltageoutput unit 340 to adjust the amount of current on the basis of theirresistance values. The reference voltage output unit 340 outputs thereference voltage VREF.

Subsequently, the operator determines whether the reference voltage VREFis equal to the target 1 voltage. In this case, the first voltagegenerating unit 10 may exhibit a voltage output characteristic shown inFIG. 5A according to temperature coefficients, and the resistor R3 ofthe reference voltage output unit 340 may exhibit a voltage outputcharacteristic shown in FIG. 5B. In addition, the second voltagegenerating unit 20 may exhibit a voltage output characteristic shown inFIG. 5C according to temperature coefficients. Therefore, even when thereference transistors M8 and K8 are exactly matched with each other, thereference voltage VREF finally output may be different from the targetvoltage due to various factors, such as the difference between thetemperature coefficients and the resistance values of the referencetransistors M8 and K8.

Therefore, when the reference voltage VREF is not equal to the targetvoltage, the operator determines whether to adjust the reference voltageVREF using the first adjusting unit 310 or the second adjusting unit 320on the basis of the difference between the voltages.

That is, when the operator determines that the difference between thereference voltage VREF and the target voltage is not large, the operatorcontrols the first adjusting unit 310 to adjust the reference voltage.On the other hand, when the operator determines that the differencebetween the reference voltage VREF and the target voltage is large, theoperator controls the second adjusting unit 320 to adjust the referencevoltage. That is, the operator determines whether the difference betweenthe voltages is in the range that can be adjusted by the first adjustingunit 310 or in the range that can be adjusted by the second adjustingunit 320.

When the difference between the reference voltage and the target voltagehas a positive value, that is, when the reference voltage VREF is higherthan the target voltage, the reference voltage VREF should be lowered bythe difference between the voltages. Since the resistance values of thetransistors are already known, the transistors having larger resistancevalues than the reference transistors M8 and K8 are connected to thereference voltage output unit 340 such that the amount of currentcorresponding to the difference between the voltages can be reduced. Incontrast, when the difference between the reference voltage and thetarget voltage has a negative value, that is, when the reference voltageVREF is lower than the target voltage, the reference voltage VREF shouldbe raised by the difference between the voltages. Since the resistancevalues of the transistors are already known, the transistors havingsmaller resistance values than the reference transistors M8 and K8 areconnected to the reference voltage output unit 340 such that the amountof current corresponding to the difference between the voltages can beincreased.

Meanwhile, when the difference between the reference voltage VREF andthe target voltage is large, the second adjusting unit 320 should becontrolled to adjust the reference voltage VREF. An operation ofadjusting the reference voltage VREF will be described below on theassumption that the transistor K1 of the second adjusting unit 320 has aresistance value capable of compensating for the difference between thevoltages.

The operator sets the logical values of the first control signals TM1,TM2, and TM3 to 0, 0, and 1, respectively, and sets the second controlsignal to a high level. In this case, a test mode may be used to set thefirst and second control signals.

The selecting unit 331 shown in FIG. 3 decodes the first control signalsand outputs the selection signal DEC1 having a high level and theselection signals DEC2 to DEC7 having low levels.

Then, the first signal output unit 332 outputs the high-level selectionsignal DEC1 to the switching element SK1 of the second adjusting unit320 on the basis of the second control signal to turn on the switchingelement SK1, which causes the transistor K1 to be connected to thereference voltage output unit 340. At that time, since the first controlsignals TM1, TM2, and TM3 have logical values of 0, 0, and 1,respectively, the third NOR gate NOR3 of the third signal output unit334 outputs a low-level signal, and the second control signal isinverted to a low level by the third inverter IV3. Therefore, the fourthNOR gate NOR4 outputs a high-level signal, and a low-level signal isoutput from the fourth inverter IV4 to the switching element SK8. As aresult, the transistor M8 is disconnected from the reference voltageoutput unit 340.

Meanwhile, since the first control signals TM1, TM2, and TM3 havelogical values of 0, 0, and 1, respectively, the first NOR gate NOR1 ofthe second signal output unit 333 outputs a low-level signal, and thesecond control signal is at a high level. Therefore, the second NOR gateNOR2 outputs a low-level signal, and a high-level signal is output fromthe second inverter IV2 to the switching element SM8. As a result, theconnection between the transistor M8 and the reference voltage outputunit 340 is maintained.

Therefore, the transistor M8 of the first adjusting unit 310 and thetransistor K8 of the second adjusting unit 320 are connected to thereference voltage output unit 340, so that they perform current controloperations according to their resistance values. As a result, thereference voltage VREF having a ZTC characteristic that is constantregardless of temperature is output, as shown in FIG. 5D.

In this embodiment, it is possible to obtain the reference voltage VREFshown in FIG. 5D by performing the adjusting operation only once sincethe difference between the voltages is checked by using the referencetransistors M8 and K8 of the first adjusting unit 310 and the secondadjusting unit 320 and the transistors whose resistance values arealready known are connected to the reference voltage output unit 340 toperform the reference voltage adjusting operation. However, in othercases, it is possible to obtain the reference voltage VREF shown in FIG.5D since only a simple change in control signal makes it possible torepeatedly perform the adjusting operation.

Second Embodiment

As shown in FIG. 6, an apparatus for generating a reference voltage in asemiconductor memory apparatus according to a second embodiment of thepresent invention includes a first voltage generating unit 10 forgenerating a voltage proportional to temperature, a second voltagegenerating unit 20 for generating a voltage inversely proportional totemperature, and a reference voltage generating unit 400 that adjuststhe amount of current in the first voltage generating unit 10 and thesecond voltage generating unit 20 in response to a control signal, so asto output a constant voltage regardless of a variation in temperature.

The reference voltage generating unit 400 includes a first adjustingunit 410 that adjusts the amount of current in the first voltagegenerating unit 10, a second adjusting unit 420 that adjusts the amountof current in the second voltage generating unit 20, a first controlunit 430 that outputs selection signals for controlling the firstadjusting unit 410, a second control unit 440 that outputs selectionsignals for controlling the second adjusting unit 420, and a referencevoltage output unit 450 that is composed of a resistor R3, and whichoutputs a reference voltage based on the amount of current adjusted bythe first adjusting unit 410 and the amount of current adjusted by thesecond adjusting unit 420.

In this embodiment, the structure of the first and second adjustingunits 410 and 420 is the same as that in the first embodiment shown inFIG. 2, and thus a detailed description thereof will be omitted.

Referring to FIG. 7A, the first control unit 430 includes a firstselecting unit 431 that outputs selection signals for adjusting theamount of current in the first voltage generating unit 10 on the basisof first control signals TM1 to TM3 and a second selecting unit 432 thatoutputs a first reference selection signal for driving a switchingelement SM8 which connects a reference transistor M8 to the referencevoltage output unit 450 when the first control signals TM1 to TM3 havepredetermined values.

The first selecting unit 431 is a decoder. The first selecting unit 431converts the first control signals into a decimal value, changes aselection signal corresponding to the converted decimal value to a highlevel, changes the other selection signals to low levels, and outputsthe selection signals.

For example, when the first control signals TM1, TM2, and TM3 havebinary values of 0, 0, and 1, respectively, and thus the decimal valuethereof is 1, a high-level signal is output to a switching element SM1and low-level signals are output to switching elements SM2 to SM7.However, the decimal value of the first control signals is set to 0(TM1=0, TM2=0, and TM3=0) during an initial reference voltagedetermining operation. When the decimal value is zero, the signalsoutput from the first selecting unit 431 to the switching elements SM1to SM7 are all at low levels. The second selecting unit 432 is formed ofa NOR gate NOR11. A high-level signal is output to a switching elementSM8 only when the decimal value of the first control signals is zero.That is, a reference transistor M8 connected to the switching elementSM8 is connected to the reference voltage output unit 450 during theinitial reference voltage determining operation.

Turning to FIG. 7B, the second control unit 440 includes a thirdselecting unit 441 that outputs selection signals for adjusting theamount of current in the second voltage generating unit 20 on the basisof second control signals TM4 to TM6 and a fourth selecting unit 442that outputs a second reference selection signal for driving a switchingelement SK8 which connects a reference transistor K8 to the referencevoltage output unit 450 when the second control signals TM4 to TM6 havepredetermined values.

The third selecting unit 441 is a decoder. The third selecting unit 441converts the second control signals TM4 to TM6 into a decimal value,changes a selection signal corresponding to the converted decimal valueto a high level, changes the other selection signals to low levels, andoutputs the selection signals.

For example, when the second control signals TM4, TM5, and TM6 havebinary values of 0, 0, and 1, respectively, and thus the decimal valuethereof is 1, a high-level signal is output to a switching element SK1,and low-level signals are output to switching elements SK2 to SK7.However, the decimal value of the second control signals is set to 0(TM4=0, TM5=0, and TM6=0) during the initial reference voltagedetermining operation. When the decimal value is zero, the signalsoutput from the third selecting unit 441 to the switching elements SK1to SK7 are all at low levels.

The fourth selecting unit 442 is formed of a NOR gate NOR12. Ahigh-level signal is output to a switching element SK8 only when thedecimal value of the second control signals is zero. That is, areference transistor K8 connected to the switching element SK8 isconnected to the reference voltage output unit 450 during the initialreference voltage determining operation.

The reference voltage output unit 450 includes the resistor R3 havingone end connected to both the first adjusting unit 410 and the secondadjusting unit 420 and the other end connected to the ground.

Next, the operation of the second embodiment having the above-mentionedstructure will be described below.

First, the operator should determine whether the reference voltagesatisfies the zero temperature coefficient (ZTC) in an initial statebefore an adjusting operation, that is, whether a target voltage isoutput regardless of temperature.

Therefore, the decimal values of the first control signals and thesecond control signals are all set to zero (TM1 to TM3=0, and TM4 toTM6=0). In this case, a test mode may be used to set the first controlsignals and the second control signals.

The first selecting unit 431 of the first selecting unit 430 shown inFIG. 7A outputs low-level signals to the switching elements SM1 to SM7since the decimal value of the first control signals is zero (TM1=0,TM2=0, and TM3=0). In addition, the third selecting unit 441 of thesecond selecting unit 440 shown in FIG. 7B outputs low-level signals tothe switching elements SK1 to SK7 since the decimal value of the secondcontrol signals is zero (TM4=0, TM5=0, and TM6=0).

Meanwhile, the NOR gate NOR11 of the second selecting unit 432 of thefirst control unit 430 outputs a high-level signal to the switchingelement SM8 since the logical values of the first control signals TM1,TM2, and TM3 are all zero. In addition, the NOR gate NOR12 of the fourthselecting unit 442 of the second control unit 440 outputs a high-levelsignal to the switching element SK8 since the logical values of thesecond control signals TM4, TM5, and TM6 are all zero.

Then, the switching elements SM8 and SK8 are turned on, which causes thereference transistors M8 and K8 to be connected to the resistor R3 ofthe reference voltage output unit 450 to perform current controloperations. As a result, the reference voltage output unit 450 outputsthe reference voltage VREF.

Subsequently, the operator determines whether the output referencevoltage VREF is equal to the target voltage. In this case, even when thereference transistors M8 and K8 are exactly matched with each other, thereference voltage VREF finally output may be different from the targetvoltage due to various factors, such as the difference between thetemperature coefficients and the resistance values of the referencetransistors M8 and K8.

When the operator determines that the difference between the referencevoltage VREF and the target voltage is very small, the operator controlsthe first adjusting unit 410 to finely adjust the reference voltage. Onthe other hand, when the operator determines that the difference betweenthe reference voltage VREF and the target voltage is large, the operatorcontrols the second adjusting unit 420 to coarsely adjust the referencevoltage. When it is difficult to generate an exact-reference voltageVREF by adjusting one of the first and second adjusting units 410 and420, the operator controls both the first and second adjusting units 410and 420 to adjust the reference voltage.

When the difference between the reference voltage and the target voltagehas a positive value, that is, when the reference voltage VREF is higherthan the target voltage, the reference voltage VREF should be lowered bythe difference between the voltages. Since the resistance values of thetransistors are already known, the transistors having larger resistancevalues than the reference transistors M8 and K8 in the first adjustingunit 410 and the second adjusting unit 420 are connected to thereference voltage output unit 450 such that the amount of currentcorresponding to the difference between the voltages can be reduced.

In contrast, when the difference between the reference voltage and thetarget voltage has a negative value, that is, when the reference voltageVREF is lower than the target voltage, the reference voltage VREF shouldbe raised by the difference between the voltages. Since the resistancevalues of the transistors are already known, the transistors havingsmaller resistance values than the reference transistors M8 and K8 inthe first adjusting unit 410 and the second adjusting unit 420 areconnected to the reference voltage output unit 450 such that the amountof current corresponding to the difference between the voltages can beincreased.

An operation of adjusting the reference voltage VREF will be describedbelow on the assumption that the transistor K1 of the second adjustingunit 420 has a resistance value capable of compensating for thedifference between the target voltage and the initial reference voltage,and the transistor M1 of the first adjusting unit 410 has a resistancevalue capable of compensating the difference between the target voltageand the reference voltage generated by adjusting the initial referencevoltage using the transistor K1.

The operator sets the decimal value of the first control signals to 1(TM1=0, TM2=0, and TM3=1), and sets the decimal value of the secondcontrol signals to 1 (TM4=0, TM5=0, and TM6=1). In this case, a testmode may be used to set the first and second control signals.

The first selecting unit 431 of the first control unit 430 decodes thefirst control signals and outputs a high-level signal to the switchingelement SM1 and low-level signals to the switching elements SM2 to SM7.When the high-level signal is output to the switching element SM1, thetransistor M1 shown in FIG. 6 is connected to the reference voltageoutput unit 450. At that time, since the first control signals TM1, TM2,and TM3 having binary values of 0, 0, and 1 are input to the secondselecting unit 432, the second selecting unit 432 outputs a low-levelsignal to the switching element SM8, which causes the transistor M8 tobe disconnected from the reference voltage output-unit 450.

The third selecting unit 441 of the second control unit 440 decodes thesecond control signals and outputs a high-level signal to the switchingelement SK1 and low-level signals to the switching elements SK2 to SK7.When the high-level signal is output to the switching element SK1, thetransistor K1 shown in FIG. 6 is connected to the reference voltageoutput unit 450. At that time, since the second control signals TM4,TM5, and TM6 having binary values of 0, 0, and 1 are input to the fourthselecting unit 442, the fourth selecting unit 442 outputs a low-levelsignal to the switching element SK8, which causes the transistor K8 tobe disconnected from the reference voltage output unit 450.

Therefore, the transistor M1 of the first adjusting unit 410 and thetransistor K1 of the second adjusting unit 420 are connected to thereference voltage output unit 450, so that they perform current controloperations according to their resistance values. As a result, thereference voltage VREF having a ZTC characteristic that is constantregardless of temperature is output.

In this embodiment, when the difference between the voltages is checked,the reference voltage adjusting operation is performed by using thereference transistors M8 and K8 of the first adjusting unit 410 and thesecond adjusting unit 420 only once by selecting the transistors whoseresistance values are already known. Therefore, it is possible to obtainthe reference voltage VREF satisfying the ZTC characteristic in oneadjusting operation. However, in other cases, it is possible to obtainthe reference voltage VREF satisfying the ZTC characteristic since onlya simple change in control signal makes it possible to repeatedlyperform the adjusting operation as well as independent control.

Although the present invention has been described in connection with theexemplary embodiments of the present invention, it will be apparent tothose skilled in the art that various modifications and changes can bemade without departing from the scope and spirit of the presentinvention. Therefore, it should be understood that the above embodimentsare not limiting, but illustrative in all aspects. The scope of thepresent invention is defined by the appended claims rather than by thedescription preceding them, and all changes and modifications that fallwithin the metes and bounds of the claims, or equivalents of such metesand bounds are therefore intended to be embraced by the claims.

According to the exemplary embodiments of the present invention, theapparatus for generating a reference voltage in a semiconductor memoryapparatus can simultaneously or independently adjust the output of aunit for generating a voltage proportional to temperature and the outputof a unit for generating a voltage inversely proportional to temperatureto generate a constant voltage regardless of a variation in temperatureand mismatch between elements. Thus, the present invention can improvethe performance and reliability of a system using the apparatus to amaximum.

1. An apparatus for generating a reference voltage in a semiconductormemory apparatus, comprising: a first voltage generating unit configuredto generate a voltage proportional to temperature; a second voltagegenerating unit configured to generate a voltage inversely proportionalto temperature; and a reference voltage generating unit configured toadjust an amount of current in the first voltage generating unit or thesecond voltage generating unit on the basis of a control signal, and tooutput a constant reference voltage regardless of a variation intemperature.
 2. The apparatus for generating a reference voltage in asemiconductor memory apparatus of claim 1, wherein the reference voltagegenerating unit includes: a first adjusting unit configured to adjustthe amount of current in the first voltage generating unit; a secondadjusting unit configured to adjust the amount of current in the secondvoltage generating unit; a control unit configured to output selectionsignals for controlling the first adjusting unit and the secondadjusting unit; and a reference voltage output unit configured to outputthe reference voltage based on the amount of current adjusted by thefirst adjusting unit and the amount of current adjusted by the secondadjusting unit.
 3. The apparatus for generating a reference voltage in asemiconductor memory apparatus of claim 2, wherein the control unitincludes: a selecting unit configured to output the selection signalsfor adjusting the -amount of current in the first voltage generatingunit or the amount of current in the second voltage generating unit by apredetermined level on the basis of first control signals; a firstsignal output unit configured to output the selection signals to thefirst adjusting unit or the second adjusting unit on the basis of asecond control signal; a second signal output unit configured to outputa first reference selection signal to the first adjusting unit on thebasis of the first control signals and the second control signal; and athird signal output unit configured to output a second referenceselection signal to the second adjusting unit on the basis of the firstcontrol signals and the second control signal.
 4. The apparatus forgenerating a reference voltage in a semiconductor memory apparatus ofclaim 3, wherein the selecting unit is a decoder.
 5. The apparatus forgenerating a reference voltage in a semiconductor memory apparatus ofclaim 3, wherein the first signal output unit includes: a first transferelement configured to output the selection signal to the secondadjusting unit on the basis of the second control signal; and a secondtransfer element configured to output the selection signal to the firstadjusting unit on the basis of the second control signal.
 6. Theapparatus for generating a reference voltage in a semiconductor memoryapparatus of claim 5, wherein the first and second transfer elements arepass gates.
 7. The apparatus for generating a reference voltage in asemiconductor memory apparatus of claim 3, wherein the number of firstsignal output units is equal to a number of bits of the selectionsignal.
 8. The apparatus for generating a reference voltage in asemiconductor memory apparatus of claim 3, wherein the first controlsignals are composed of a combination of two or more test mode signals.9. The apparatus for generating a reference voltage in a semiconductormemory apparatus of claim 3, wherein, when the first control signalshave specific values and when the second adjusting unit is selected bythe second control unit, the second signal output unit outputs the firstreference selection signal to the first adjusting unit.
 10. Theapparatus for generating a reference voltage in a semiconductor memoryapparatus of claim 3, wherein the second signal output unit includes: afirst NOR gate configured to receive the first control signals as inputand having an output; and a second NOR gate configured to receive theoutput of the first NOR gate and the second control signal as input andto output a logical value thereof to a switching element.
 11. Theapparatus for generating a reference voltage in a semiconductor memoryapparatus of claim 3, wherein, when the first control signals havespecific values and when the first adjusting unit is selected by thesecond control unit, the third signal output unit outputs the secondreference selection signal to the second adjusting unit.
 12. Theapparatus for generating a reference voltage in a semiconductor memoryapparatus of claim 3, wherein the third signal output unit includes: afirst NOR gate configured to receive the first control signals as inputand having an output; and a second NOR gate configured to receive theoutput of the first NOR gate and an inverted signal of the secondcontrol signal as inputs and to output a logical value thereof to aswitching element.
 13. The apparatus for generating a reference voltagein a semiconductor memory apparatus of claim 2, wherein the firstvoltage generating unit includes a reference voltage output terminal anda power supply terminal and the first adjusting unit includes aplurality of current control elements connected between the referencevoltage output terminal and the power supply terminal through theswitching elements.
 14. The apparatus for generating a reference voltagein a semiconductor memory apparatus of claim 13, wherein the pluralityof current control elements have different resistance values.
 15. Theapparatus for generating a reference voltage in a semiconductor memoryapparatus of claim 13, wherein the plurality of current control elementsare connected in series to one another either in an ascending ordescending order of resistance values.
 16. The apparatus for generatinga reference voltage in a semiconductor memory apparatus of claim 13,wherein the plurality of current control elements are transistors. 17.The apparatus for generating a reference voltage in a semiconductormemory apparatus of claim 2, wherein the first voltage generating unitincludes a reference voltage output terminal and a power supply terminaland the second adjusting unit includes a plurality of current controlelements connected between the reference voltage output terminal and thepower supply terminal of the first voltage generating unit through theswitching elements.
 18. The apparatus for generating a reference voltagein a semiconductor memory apparatus of claim 17, wherein the pluralityof current control elements have different resistance values.
 19. Theapparatus for generating a reference voltage in a semiconductor memoryapparatus of claim 17, wherein the plurality of current control elementsare connected in series to one another either in an ascending ordescending order of resistance values.
 20. The apparatus for generatinga reference voltage in a semiconductor memory apparatus of claim 17,wherein the plurality of current control elements are transistors. 21.The apparatus for generating a reference voltage in a semiconductormemory apparatus of claim 2, wherein the reference voltage output unitincludes a resistor having one end connected to both the first adjustingunit and the second adjusting unit and an other end connected to ground.22. An apparatus for generating a reference voltage in a semiconductormemory apparatus, comprising: a first voltage generating unit configuredto generate a voltage proportional to temperature; a second voltagegenerating unit configured to generate a voltage inversely proportionalto temperature; and a reference voltage generating unit configured toseparately adjust an amount of current in the first voltage generatingunit and the second voltage generating unit on the basis of first andsecond control signals, and to output a constant reference voltageregardless of a variation in temperature.
 23. The apparatus forgenerating a reference voltage in a semiconductor memory apparatus ofclaim 22, wherein the reference voltage generating unit includes: afirst adjusting unit configured to adjust the amount of current in thefirst voltage generating unit; a second adjusting unit configured toadjust the amount of current in the second voltage generating unit; afirst control unit configured to output selection signals forcontrolling the first adjusting unit; a second control unit configuredto output selection signals for controlling the second adjusting unit;and a reference voltage output unit that outputs the reference voltagebased on the amount of current adjusted by the first adjusting unit andthe amount of current adjusted by the second adjusting unit.
 24. Theapparatus for generating a reference voltage in a semiconductor memoryapparatus of claim 23, wherein the first voltage generating unitincludes a reference voltage output terminal and a power supply terminaland the first adjusting unit includes a plurality of current controlelements connected between the reference voltage output terminal and thepower supply terminal through switching elements.
 25. The apparatus forgenerating a reference voltage in a semiconductor memory apparatus ofclaim 24, wherein the plurality of current control elements havedifferent resistance values.
 26. The apparatus for generating areference voltage in a semiconductor memory apparatus of claim 24,wherein the plurality of current control elements are connected inseries to one another either in an ascending or descending order ofresistance values.
 27. The apparatus for generating a reference voltagein a semiconductor memory apparatus of claim 24, wherein the pluralityof current control elements are transistors.
 28. The apparatus forgenerating a reference voltage in a semiconductor memory apparatus ofclaim 23, wherein the first voltage generating unit includes a referencevoltage output terminal and a power supply terminal and the secondadjusting unit includes a plurality of current control elementsconnected between the reference voltage output terminal and the powersupply terminal through switching elements.
 29. The apparatus forgenerating a reference voltage in a semiconductor memory apparatus ofclaim 28, wherein the plurality of current control elements havedifferent resistance values.
 30. The apparatus for generating areference voltage in a semiconductor memory apparatus of claim 28,wherein the plurality of current control elements are connected inseries to one another either in an ascending or descending order ofresistance values.
 31. The apparatus for generating a reference voltagein a semiconductor memory apparatus of claim 28, wherein the pluralityof current control elements are transistors.
 32. The apparatus forgenerating a reference voltage in a semiconductor memory apparatus ofclaim 23, wherein the first control unit includes: a first selectingunit configured to output selection signals for adjusting the amount ofcurrent in the first voltage generating unit by a predetermined level onthe basis of the first control signals; and a second selecting unitconfigured to output a first reference selection signal on the basis ofthe first control signals.
 33. The apparatus for generating areference-voltage in a semiconductor memory apparatus of claim 32,wherein the first selecting unit is a decoder configured to decode thefirst control signals and outputs the selection signals for adjustingthe amount of current in the first voltage generating unit on the basisof the decoded signals.
 34. The apparatus for generating a referencevoltage in a semiconductor memory apparatus of claim 32, wherein thesecond selecting unit is a NOR gate configured to receive the firstcontrol signals as input and to output the first reference selectionsignal on the basis the received first control signals.
 35. Theapparatus for generating a reference voltage in a semiconductor memoryapparatus of claim 23, wherein the second control unit includes: a firstselecting unit configured to output selection signals for adjusting theamount of current in the second voltage generating unit by apredetermined level on the basis of the second control signals; and asecond selecting unit configured to output a second reference selectionsignal on the basis of the second control signals.
 36. The apparatus forgenerating a reference voltage in a semiconductor memory apparatus ofclaim 35, wherein the first selecting unit is a decoder configured todecode the second control signals and to output the selection signalsfor adjusting the amount of current in the second voltage generatingunit on the basis of the decoded signals.
 37. The apparatus forgenerating a reference voltage in a semiconductor memory apparatus ofclaim 35, wherein the second selecting unit is a NOR gate configured toreceive the second control signals as input and to output the secondreference selection signal on the basis of the received second controlsignals.
 38. The apparatus for generating a reference voltage in asemiconductor memory apparatus of claim 23, wherein the referencevoltage output unit includes a resistor having one end connected to boththe first adjusting unit and the second adjusting unit and the other endconnected to the ground.